The present invention relates to the electrical and electronic arts, and more specifically, to semiconductor fabrication techniques and the like.
For quite some time, continued reduction in the size of metal oxide semiconductor field effect transistors (MOSFETs) has driven progress in the semiconductor industry. Despite predictions of barriers to continued progress, improvements in accordance with Moore's Law have continued apace. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs (and therefore complementary metal oxide semiconductor (CMOS) performance) through continued scaling, further methods for improving performance, in addition to scaling, have become important.
One approach is the use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs). FinFETs are non-planar semiconductor devices which include at least one semiconductor fin protruding from a surface of a substrate; they can increase the ON-current per unit area relative to planar field effect transistors.
Semiconductor fins are typically formed utilizing a sidewall image transfer (SIT) process, since the same provides sub-lithographic line widths. In a typical SIT process, spacers are formed on each sidewall surface of a sacrificial mandrel that is formed on a topmost semiconductor material of a substrate. The sacrificial mandrel is removed and the remaining spacers are used as an etch mask to etch the topmost semiconductor material of the substrate. The spacers are then removed after each semiconductor fin has been formed.
One problem that is associated with forming semiconductor fins at tight pitch is that the process window for the cutting of the unwanted semiconductor fins is quite narrow. More specifically, the space available between fins at a tight pitch decreases the process window for placement of fin cut mask edge in between fins. One approach to address this issue is set forth in co-assigned U.S. Pat. No. 9,305,845 of Colburn et al., which discloses a self-aligned quadruple patterning (SAQP) process. While techniques of the Colburn patent have represented a substantial advance in the state of the art, nevertheless, in some instances, there are dummy fins that cannot be easily cleaned up because they are too close to adjacent active fins. U.S. Pat. No. 9,305,845 of Colburn et al. is hereby expressly incorporated herein by reference in its entirety for all purposes.